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Practical 6

To design a 4x4 memory system using 1x1 memory chips in COA Virtual Lab (IIT Kharagpur).

Theory

  1. What is the difference between memory capacity and memory organization?
  2. How do you calculate the number of address lines required for a 4x4 memory system?
  3. Explain the role of address decoders in memory chip selection.
  4. How are 1x1 memory chips interconnected to form a larger memory system?
  5. What are the advantages of using modular memory design with smaller chips?

Virtual Lab Simulation

Access the COA Virtual Lab at IIT Kharagpur:

COA Virtual Lab

Steps to Design 4x4 Memory

  1. Open the Memory Design experiment in COA Virtual Lab
  2. Select 1x1 memory chips from the component library
  3. Arrange 16 chips in a 4x4 matrix configuration
  4. Connect address lines A0 and A1 to row decoder
  5. Connect address lines A2 and A3 to column decoder
  6. Wire the data input/output lines
  7. Add control signals (Read/Write, Chip Select)
  8. Test the memory system with different address inputs
  9. Verify read and write operations

Memory Organization

The 4x4 memory system requires:

 Total Memory Cells: 16 (4 rows × 4 columns)
 Address Lines: 4 (A3, A2, A1, A0)
 Data Lines: 1 (for 1-bit data)
 Control Lines: Read/Write, Chip Select

 Address Decoding:
 A1 A0 → Row Select (0-3)
 A3 A2 → Column Select (0-3)